The present invention relates to data decoding, and more particularly, to a method and apparatus of decoding an encoded data frame (e.g., an encoded FACCH frame) including dummy bit sequences each generated from encoding a predetermined bit pattern (e.g., 0x2B from least significant bit LSB to most significant bit MSB).
In digital communication systems, the maximum likelihood decoding is a popular technique applied in numerous communication systems with different architectures. The Viterbi decoder is a generalized functional block utilizing this technique to decode the received data frame which might include errors introduced by many factors. As it is well known in the art, additive white Gaussian noise (AWGN) and many sources of interference exist in general communication channels. To reduce the error rate of signal detection, most communication systems encode the data and then transmit the encoded data instead of transmitting the original data directly. This encoding procedure comprises convoluting the data according to a specific coding algorithm, where the number of bits of the encoded data is more than the original data. For example, convolutional codes are generate by encoding the original data according to a code rate equal to k/n, where n represents the number of output bits and k represents the number of input bits. When a receiver end decodes the received encoded data, the receiver end examines the accuracy of the received encoded data by using the maximum likely-hood decoding (i.e., the Viterbi decoding) to compute a metric value for each path and then make a decision based upon the accumulated path metric values. As the Viterbi decoding is well known to those skilled in this art, further description is omitted here for the sake of brevity.
For certain communication channels in a communication system, dummy bits or filling bits are padded to the data bits to be transmitted when the data length of the data bits is shorter than a predetermined value. That is, the filling bits are added when there is not so much information to be transmitted via the communication channel. Taking the fast associated control channel (FACCH) in a GSM communication system for example, each encoded FACCH frame is composed of 456 encoded bits. Please refer to FIG. 1, which is a diagram illustrating an encoding architecture for the FACCH frame. The information source 12 provides data bits (184 bits or 23 bytes) to be transmitted via the FACCH channel. The error checking block 14 then calculates CRC bits (40 bits or 5 bytes) according to the data bits, and then adds the CRC bits following the data bits to generate a resultant data frame of 224 bits. In the end, the convolutional encoding block 16, which is configured to have a code rate of 1/2, performs a convolutional encoding according to the raw data frame (224 bits) and 4 tail bits to output a convolutional encoding result, e.g., the encoded FACCH frame. When the data length of the data bits is shorter than 184, a predetermined bit pattern of filling bits is repeatedly added until the resultant data length reaches 184. Regarding the FACCH frame, the above predetermined bit pattern is 0x2B, i.e. (1,1,0,1,0,1,0,0) from least significant bit (LSB) to most significant bit (MSB). Please refer to FIG. 2. FIG. 2 is a diagram illustrating a resultant data frame including the filling bits appended to the raw data bits.
Regarding the conventional decoder architecture, the Viterbi decoder is responsible for decoding the encoded FACCH frame having 456 bits to extract the control message carried therewith. In some situations, however, if the error bits presented in the middle of the encoded FACCH frame that is generated from encoding the filling bits might make the decoder fail to recover the raw FACCH frame from the encoded FACCH frame. As a result, the conventional Viterbi decoder discards this decoding result of the encoded FACCH frame, and then indicates a decoding failure accordingly. It should be noted that the above-mentioned encoded FACCH frame might include correct encoded bits corresponding to the raw data bits and CRC bits; however, a decoding failure may occur due to the error bits corresponding to the filling bit portion. Therefore, a method and apparatus is required to correct encoded FACCH frame containing error bits present in the filling bit portion to increase probability for successfully acquiring encoded FACCH frame.